Former Intel CEO: The Golden Age of Hardware Startups Has Arrived

At a time when AI compute demand is exploding, hardware startups are facing unprecedented opportunities. In a recent in-depth interview, former Intel CEO Pat Gelsinger put it bluntly: "For hardware people, this is like a renaissance." The industry veteran, who once led the design of the 486 processor and helmed both Intel and VMware, now serves as a general partner at Playground Global and shared his sharp insights on hardware innovation in the AI era.

Energy: The Hard Constraint of the AI Era

"In the AI digital age, energy capacity equals economic capacity." Gelsinger's opening remark cut straight to the core. He warned that if you cannot power data centers, buying a million GPUs is meaningless. "You're going to see more and more data center projects default because the energy simply can't keep up."

According to Gelsinger's analysis, US energy capacity has been nearly stagnant for the past 15 years. Although it has improved somewhat in the last five years, annual growth is only about 4%. Gas turbine lead times run as long as eight years, and nuclear power has not built a new reactor in twenty years. This energy bottleneck is becoming the ceiling on AI euphoria. He specifically noted that 800-volt DC data centers and vertical gallium nitride (GaN) power conversion technologies will reshape power delivery architectures: "Edison's revenge has arrived."

800-volt DC data centers refers to changing the data center power distribution architecture from traditional alternating current (AC) supply to direct 800V direct current (DC) supply. Traditional data centers go through multiple AC-DC and DC-DC conversions, each with energy losses; an 800V DC architecture can reduce conversion stages, lower losses, and cut copper cable usage (at high voltage, current is lower for the same power). This approach is being standardized in organizations such as OCP (Open Compute Project), and vendors including NVIDIA have announced support for 800V DC racks.

Vertical gallium nitride (GaN) power conversion refers to power devices made from gallium nitride material with a vertical structure (current flows vertically) rather than the traditional lateral structure. Compared with silicon, GaN has a higher breakdown field and lower switching losses, making it suitable for high-frequency, high-voltage scenarios; a vertical structure can withstand higher voltages and larger currents while also dissipating heat better. Such devices are considered key to improving efficiency across the entire chain from the grid to GPU board-level power delivery, and are especially well suited to 800V DC architectures.

The Bottleneck in Chip Design Has Shifted

AI tools are drastically compressing chip design time, but Gelsinger points out that the bottleneck has simply moved to manufacturing. "I can design it in three months, but it takes nine months to get silicon back." He laid out the math: three months of design, three months of tapeout, three months of advanced packaging, plus rack-level integration—"a chip is no longer a chip; it's the entire rack."

When the design cycle shrinks to three months while the manufacturing cycle stretches to nine months, "your understanding of the AI workload may already be outdated." Citing GraphCore as an example, Gelsinger noted that even if the design wasn't bad, the world had already changed. He believes new lithography technologies and cheaper prototyping processes are needed to compress the manufacturing cycle to one or two months.

Memory Innovation: The Biggest Shift in Thirty Years

"Over the past 30 years, how many truly new memory architectures have we had? Zero." Gelsinger recalled that beyond DRAM, SRAM, and flash, there have been no breakthroughs. He personally participated in the development of at least five new memory architectures, including Intel's Optane, but none succeeded.

However, things are changing. All three major memory manufacturers are now among the global top 20 by market capitalization, and the memory industry's market value has grown by about $2.5 trillion over the past four years. "The combined demand from capital and technology has finally made memory innovation profitable." Gelsinger revealed that he has just invested in a new memory company still in stealth mode, and he is bullish on directions such as ferroelectric materials and non-capacitive high-density storage.

As for HBM, he bluntly called it "ugly but our best option." Shoreline bandwidth limits, power consumption, and thermal issues make it unsustainable. He believes the future lies in integrating memory more tightly with compute, but the number of stacked layers will not increase indefinitely. "Three to five layers may be the sweet spot; 16-layer stacks are nearly impossible from a yield standpoint."

He described a typical stack of about eight layers: compute die, memory stack, power layer, RDL routing, plus optical I/O and III-V materials. "It's both an engineering feat and a manufacturing nightmare."

HBM (High Bandwidth Memory) is a memory technology that vertically stacks multiple DRAM dies using through-silicon vias (TSVs) and packages them adjacent to a GPU/accelerator via a silicon interposer. It trades an extremely wide parallel interface for high bandwidth and low power, and is now standard in AI training chips. But HBM's limitations are obvious: stack layer count is constrained by yield and heat dissipation, interposer area limits capacity scaling, and the "shoreline" (the perimeter of the chip edge available for routing) limits how many HBM stacks a single die can connect to.

Ferroelectric materials refer to materials with spontaneous polarization whose polarization direction can be flipped by an external electric field. When used for storage, their polarization state can non-volatilely represent 0/1, theoretically combining DRAM-like speed with flash-like non-volatility and low write energy. In recent years, hafnium-based ferroelectric thin films (HfO₂ doping) compatible with CMOS processes have brought ferroelectric memory (FeRAM/FeFET) back into focus, and it is seen as one candidate for breaking through the scaling limits of traditional capacitive DRAM.

A Hundred Contenders Will Eventually Converge

There are currently hundreds of AI inference chip startups, which Gelsinger considers unsustainable. "No industry in history has ever had 100 processor suppliers." He gave three reasons for convergence: extreme specialization of workloads is unsustainable; model architectures are still evolving rapidly; and economies of scale will ultimately eliminate most players.

But he also acknowledged that AI coding tools could change how software ecosystems are built. "If agent swarms can generate optimized kernels overnight, then the software barrier to hardware diversity is lowered." Still, he insisted that manufacturing scale, capital requirements, and customer lock-in effects will drive industry consolidation.

Optical Interconnects and Network Architecture

"I declared the death of copper interconnects 25 years ago, and one day I'll be right." Gelsinger joked. He believes all I/O should move to optics, but the core compute-memory complex should remain electrically interconnected internally. In current scale-up environments, copper cables are becoming ever-shorter waveguides, and the cost of a five-meter copper cable already exceeds that of a hundred-meter fiber link.

He expects large-scale deployment of co-packaged optics (CPO) in 2028-2029. On network architecture, he agrees with Stanford professor Nick McKeown: AI traffic is highly predictable and closer to circuit switching than packet switching. "Optical circuit switching (OCS) is the right direction, and the boundary between scale-up and scale-out will gradually blur."

Co-packaged optics (CPO) refers to packaging the optical engine (laser, modulator, photodetector) on the same substrate as the switch chip or compute chip, rather than plugging it into a faceplate port like a traditional optical module. This greatly shortens electrical signal traces, reduces power consumption and latency, and increases faceplate port density. The challenges lie in laser thermal management, serviceability (a failed optical engine cannot be hot-swapped as easily as an optical module), and packaging yield. The industry generally expects CPO to enter large-scale deployment around 2028, when speeds rise above 1.6T.

Optical circuit switching (OCS) refers to switching light paths directly in the optical domain without converting optical signals to electrical signals for forwarding. Typical implementations include MEMS micromirror arrays and liquid crystal on silicon (LCoS). Because AI training traffic has highly predictable regularity (such as the fixed communication pattern of all-reduce), OCS can pre-establish light paths like circuit switching, eliminating the power and latency of per-packet processing. Google has already deployed OCS in its TPU clusters.

Implications for Hardware Entrepreneurs

Gelsinger's assessment maps out clear opportunities for hardware entrepreneurs: energy infrastructure (nuclear power, power conversion, cooling), memory innovation (new materials, 3D integration), optical interconnects (CPO, optical switching), and virtualization platforms for agents. He particularly emphasized that VMware's abstraction model needs to be rebuilt for the agent era: "vMotion for agents—every virtualization concept will have a new incarnation."

When asked whether this is the best time for hardware startups, Gelsinger answered without hesitation: "Absolutely yes. Energy, memory, packaging, optics, power—every layer is being reinvented." After AI pushed software innovation to its limits, hardware is back at center stage.

vMotion is VMware's live migration technology for virtual machines, which can move a running VM from one physical server to another without downtime, relying on complete abstraction of CPU state, memory, and storage. What Gelsinger means by "vMotion for agents" is that agents, as a new unit of compute workload, will likewise need a similar abstraction layer—capable of migrating, pausing, snapshotting, and restoring across different hardware and different clouds while keeping context and state consistent. This means the virtualization layer needs to expand from "abstracting machines" to "abstracting agent workloads," involving new problems such as state serialization, reconstruction of tool-calling environments, and security isolation.