AHRR
An AI agent-driven chip design workflow that combines high-level synthesis (HLS) abstraction with RTL refinement optimization. It first constructs designs rapidly at a high level of abstraction and then returns to the RTL level to exploit lower-level optimization opportunities, achieving a 2.6× speedup over direct RTL design on multi-task benchmarks.
Timeline (last 90 days)
By introducing High-Level Synthesis (HLS) as the agent's working level combined with RTL-level refinement, the research team achieved an average geometric mean speedup of 2.6× over direct RTL design on multi-task benchmarks.
The research team designed and compared four workflows: direct RTL design, agent-based HLS design, post-compilation HLS refinement, and post-HLS RTL refinement.
The paper's core contribution, AHRR (Agent-based HLS with RTL Refinement), combines agent-based HLS design with post-HLS RTL refinement, forming a workflow that first constructs the design at a high level of abstraction and then returns to the RTL layer to reclaim low-level optimization opportunities.
The paper claims that the design flow trade-offs studied are largely independent of the target process, and the AHRR approach is expected to transfer to other chip implementation paths such as ASIC.
The research team has open-sourced the code and evaluation artifacts for AHRR (GitHub: ZijD/AHRR).
All Facts (5)
By introducing High-Level Synthesis (HLS) as the agent's working level combined with RTL-level refinement, the research team achieved an average geometric mean speedup of 2.6× over direct RTL design on multi-task benchmarks.
50%UnverifiedThe research team designed and compared four workflows: direct RTL design, agent-based HLS design, post-compilation HLS refinement, and post-HLS RTL refinement.
50%UnverifiedThe paper's core contribution, AHRR (Agent-based HLS with RTL Refinement), combines agent-based HLS design with post-HLS RTL refinement, forming a workflow that first constructs the design at a high level of abstraction and then returns to the RTL layer to reclaim low-level optimization opportunities.
50%UnverifiedThe paper claims that the design flow trade-offs studied are largely independent of the target process, and the AHRR approach is expected to transfer to other chip implementation paths such as ASIC.
50%UnverifiedThe research team has open-sourced the code and evaluation artifacts for AHRR (GitHub: ZijD/AHRR).
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