DRAM

HBM is a packaging technology that vertically stacks multiple layers of DRAM chips through Through-Silicon Via (TSV) technology and integrates them with the GPU via a silicon interposer.

HBM achieves high-density interlayer interconnection by vertically stacking multiple layers of DRAM chips using through-silicon via (TSV) technology, delivering memory bandwidth up to 3–5 times higher than conventional GDDR6 memory, while consuming less power and occupying a smaller package footprint.

4F² is a measure of area efficiency for DRAM memory chips, meaning each memory cell occupies only 4 times the minimum feature size in area, representing the theoretical limit of storage density, while mainstream DRAM today typically ranges between 6F² and 8F².

The complex manufacturing process and difficult yield ramp-up of HBM have led to persistently tight supply.

Flash chips provide far greater storage density per unit area than DRAM at a much lower cost

A tiered memory architecture organizes HBM, DRAM, and CXL extended memory pools into a hierarchical structure, with HBM serving as the high-speed cache layer, DRAM as the main memory layer, and CXL providing large-capacity shareable memory resources.

HBM uses TSV technology to drill thousands of micron-scale through-holes in extremely thin DRAM wafers, requiring each DRAM die layer to be ground down to approximately 30–40 micrometers in thickness.

The growing demand for HBM from AI servers will directly crowd out the general-purpose capacity of DRAM production lines, thereby increasing the overall supply tightness of memory chips.

Micron's main operations in Taiwan are concentrated in DRAM manufacturing.

In the past 30 years, aside from DRAM, SRAM, and flash memory, no successful new memory architecture has emerged.

The memory market is cyclical, stemming from supply-demand mismatch: DRAM and NAND are standardized commodity products, manufacturers' capacity expansion cycles are long (2-3 years), while demand-side fluctuations are large.

The MemSilicon team originates from the team of Academician Liu Ming of the Chinese Academy of Sciences, has more than twenty years of accumulated memory technology expertise, and has research foundations in areas including RRAM, SRAM, MRAM, and DRAM.

The US Department of Commerce's Bureau of Industry and Security (BIS) administers semiconductor equipment through lists under the Export Administration Regulations (EAR), with advanced logic chips (such as 7 nanometers and below) placed in the highest control tier, while memory chips such as NAND and DRAM are generally not regarded as the areas most directly related to national security.

NAND and DRAM are together the two mainstream types of memory chips, but NAND focuses on capacity and persistent storage, while DRAM focuses on high-speed temporary reading and writing.

Memory (DRAM) is a cyclical commodity whose price fluctuates frequently under the combined influence of production capacity, demand, and market inventory.

Between 2022 and 2023, DRAM prices experienced a decline of more than 50%.

DRAM price cycles are often attributed to the pork cycle effect: when prices are high, manufacturers expand capacity; once capacity is released, prices plummet; manufacturers then cut investment, supply contracts, and prices rise again.

Rising memory prices force device manufacturers to absorb higher bill-of-materials costs or configure lower-capacity memory within the same budget.

HBM is derived from standard DRAM processes, and producing HBM consumes a large amount of wafer capacity that could otherwise be used for ordinary DRAM

Flash memory has inherent advantages over DRAM in capacity density and cost, but has disadvantages in write endurance and latency.