N2P
A performance-enhanced variant in TSMC's 2-nanometer family, a derivative process following the N2 node. It further optimizes the gate-all-around (GAA) nanosheet transistors introduced in N2, typically offering performance or energy-efficiency gains ranging from a few percentage points to about ten percent.
Timeline (last 90 days)
Maia 300 uses a multi-chiplet design: the compute chiplet is based on TSMC's N2P process, while the memory controllers and I/O functions are placed on separate dies.
Maia 300 is equipped with 8 HBM4 memory stacks, uses compute chiplets manufactured on TSMC's N2P process, and is deployed in the form of 96-accelerator racks.
All Facts (2)
Maia 300 uses a multi-chiplet design: the compute chiplet is based on TSMC's N2P process, while the memory controllers and I/O functions are placed on separate dies.
50%UnverifiedMaia 300 is equipped with 8 HBM4 memory stacks, uses compute chiplets manufactured on TSMC's N2P process, and is deployed in the form of 96-accelerator racks.
50%