Unverified50% confidenceFactExact time
Developers compiled a complete RISC-V CPU architecture into the model weights of Qwen 3.5 4B, using the Gated DeltaNet layers as an exact memory model, enabling programs to run without error through forward propagation alone, raising the arithmetic benchmark from 48% to a perfect 100%.
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50%
Confidence
Long-term
Relevance
10/29/2026
First Seen
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Related Claims
UnverifiedA project called Qwenputer embeds the behavior of a 32-bit RISC-V CPU into the weights of the Qwen3.5-4B model, enabling the model to execute RISC-V instructions rather than calling an external emulator.73% similarUnverifiedQwen 3.8 27B adopts a hybrid architecture in which, across 64 layers, the majority use Gated DeltaNet layers with Gated Full Attention layers interspersed at regular intervals.70% similarUnverifiedNVIDIA engineers, by writing a brand-new dedicated fused decoding kernel upstream for VLLM, achieved a throughput of 423 tokens per second per user on the 280-billion-parameter Kimi K3 model, a 1.68x speedup on equivalent hardware.69% similarUnverifiedThe Qwen3.5 flagship 397B-A17B adopts a hybrid architecture that combines Gated Delta Networks with sparse Mixture-of-Experts (MoE), activating only 17 billion parameters per token.69% similarUnverifiedFreeToken's Q* strategy measures the machine's PCIe bandwidth and RAM speed in real time, dynamically deciding whether each batch of missing experts should be transferred from RAM to the GPU or computed directly on the CPU.67% similar
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