Unverified50% confidenceFactExact time
GPU global memory access latency can reach hundreds of clock cycles, while on-chip shared memory latency is only tens of cycles.
1
Sources
50%
Confidence
Long-term
Relevance
9/16/2026
First Seen
Sources
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Related Claims
UnverifiedThe GPU multi-level memory hierarchy from highest to lowest is: register file (latency ~1 cycle), shared memory/L1 cache (~32–228 KB, latency ~20–40 cycles), L2 cache (H100 ~50 MB, latency ~200 cycles), and HBM global memory (latency ~500–800 cycles).77% similarUnverifiedGPU的SM能同时驻留的Warp数量决定了GPU隐藏内存访问延迟的能力，制约Occupancy的核心资源是寄存器文件与共享内存74% similarUnverifiedGPU上下文切换需保存完整GPU状态（包括寄存器文件、共享内存和L1缓存），数据量可达数百MB，而CPU上下文切换仅需保存几KB74% similarUnverifiedAn extremely large prompt may completely occupy the GPU for several minutes during the prefill phase, causing queue congestion when multiple users run full-context tasks simultaneously.71% similarUnverifiedGPU solutions use batching technology to combine multiple user requests for computation, which can greatly increase overall throughput and represents a trade-off between latency and throughput.71% similar
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