Unverified70% confidenceFactExact time
The GPU multi-level memory hierarchy from highest to lowest is: register file (latency ~1 cycle), shared memory/L1 cache (~32–228 KB, latency ~20–40 cycles), L2 cache (H100 ~50 MB, latency ~200 cycles), and HBM global memory (latency ~500–800 cycles).
2
Sources
70%
Confidence
Long-term
Relevance
7/7/2026
First Seen
Sources
Related Claims
VerifiedThe GPU memory hierarchy from fastest to slowest is: registers, L1 cache/shared memory, L2 cache, global memory (VRAM).85% similarUnverifiedGPU上下文切换需保存完整GPU状态（包括寄存器文件、共享内存和L1缓存），数据量可达数百MB，而CPU上下文切换仅需保存几KB78% similarUnverifiedGPU global memory access latency can reach hundreds of clock cycles, while on-chip shared memory latency is only tens of cycles.77% similar
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